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| author | Matt Turner <mattst88@gmail.com> | 2015-06-02 17:46:38 -0700 |
|---|---|---|
| committer | Matt Turner <mattst88@gmail.com> | 2015-06-03 10:47:41 -0700 |
| commit | d46d04529b9c1e55b4c3b65a7078bbbd7ab1a810 (patch) | |
| tree | 150aa74a8f99bcd915aee57a9c5d7281a93daa50 /src/mesa/drivers/dri/i965/brw_fs_generator.cpp | |
| parent | 54a70a8ef20a9a875f0828acb42332cf69217ff5 (diff) | |
| download | external_mesa3d-d46d04529b9c1e55b4c3b65a7078bbbd7ab1a810.zip external_mesa3d-d46d04529b9c1e55b4c3b65a7078bbbd7ab1a810.tar.gz external_mesa3d-d46d04529b9c1e55b4c3b65a7078bbbd7ab1a810.tar.bz2 | |
i965: Use UW-typed immediate in multiply inst.
Some hardware reads only the low 16-bits even if the type is UD, but
other hardware like Cherryview can't handle this.
Fixes spec@arb_gpu_shader5@execution@sampler_array_indexing@fs-simple on
Cherryview.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90830
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_generator.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 40a3db3..ff05b2a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -788,7 +788,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src brw_set_default_access_mode(p, BRW_ALIGN_1); /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */ - brw_MUL(p, addr, sampler_reg, brw_imm_ud(0x101)); + brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101)); if (base_binding_table_index) brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index)); brw_AND(p, addr, addr, brw_imm_ud(0xfff)); |