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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-02-10 17:22:45 -0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-02-11 21:41:58 -0800 |
| commit | e93566a15c61c33faa2e694aa18d18e544e857ff (patch) | |
| tree | 1e413c8afd75657f82ddc8bf5591e2b83eda9503 /src/mesa/drivers/dri/i965/brw_fs_generator.cpp | |
| parent | cba6a4a12943d635e8dd3d38d94e21cbcab8be34 (diff) | |
| download | external_mesa3d-e93566a15c61c33faa2e694aa18d18e544e857ff.zip external_mesa3d-e93566a15c61c33faa2e694aa18d18e544e857ff.tar.gz external_mesa3d-e93566a15c61c33faa2e694aa18d18e544e857ff.tar.bz2 | |
i965/vs/skl: Use vec4 datatypes for message header
We're using a SIMD4x2 sampler message, which has execsize 4, and so the
register width must be <= 4. Use <4,4,1> regioning instead of <8,8,1>
regioning to access the same data but avoid tripping the assert.
Fixes the following piglit tests:
spec/glsl-1.20/compiler/structure-and-array-operations/array-selection.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-basic.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-struct.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-function.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-array.vert
glslparsertest/glsl2/condition-07.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-variable.vert
v2: Better commit message courtesy of Ken.
I had a discussion with Ken, and we both question how we end up with a mov and
execsize 4. For now though, this fixes the piglit tests, so we can worry about
it later.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_generator.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 8cd36f8..f7b8771 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1024,13 +1024,13 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst, if (brw->gen >= 9) { /* Skylake requires a message header in order to use SIMD4x2 mode. */ - src = retype(brw_vec8_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD); + src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD); mlen = 2; header_present = true; brw_push_insn_state(p); brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, src, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + brw_MOV(p, src, retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD)); brw_set_default_access_mode(p, BRW_ALIGN_1); brw_MOV(p, get_element_ud(src, 2), |