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author | Matt Turner <mattst88@gmail.com> | 2015-04-02 16:15:53 -0700 |
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committer | Matt Turner <mattst88@gmail.com> | 2015-04-21 09:24:48 -0700 |
commit | fde3100fe65a175f034c77e7989601839c9983bb (patch) | |
tree | 64ce6edd25c7b9af90ad6f92da97353e57e8db70 /src/mesa/drivers/dri/i965/brw_fs_generator.cpp | |
parent | b14313e45295d91b5737775ec788c76d8f0c2f93 (diff) | |
download | external_mesa3d-fde3100fe65a175f034c77e7989601839c9983bb.zip external_mesa3d-fde3100fe65a175f034c77e7989601839c9983bb.tar.gz external_mesa3d-fde3100fe65a175f034c77e7989601839c9983bb.tar.bz2 |
i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.
These were used only on Gen4 and 5. emit_interpolation_setup_gen6() emits
ADDs directly. The virtual opcodes weren't providing anything useful.
I'm going to repurpose these opcodes, so deleting and readding them makes
it simpler to see what's going on.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_generator.cpp')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 397d825..353f35a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -387,40 +387,6 @@ fs_generator::generate_blorp_fb_write(fs_inst *inst) inst->header_present); } -/* Computes the integer pixel x,y values from the origin. - * - * This is the basis of gl_FragCoord computation, but is also used - * pre-gen6 for computing the deltas from v0 for computing - * interpolation. - */ -void -fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x) -{ - struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); - struct brw_reg src; - struct brw_reg deltas; - - if (is_x) { - src = stride(suboffset(g1_uw, 4), 2, 4, 0); - deltas = brw_imm_v(0x10101010); - } else { - src = stride(suboffset(g1_uw, 5), 2, 4, 0); - deltas = brw_imm_v(0x11001100); - } - - if (dispatch_width == 16) { - dst = vec16(dst); - } - - /* We do this SIMD8 or SIMD16, but since the destination is UW we - * don't do compression in the SIMD16 case. - */ - brw_push_insn_state(p); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_ADD(p, dst, src, deltas); - brw_pop_insn_state(p); -} - void fs_generator::generate_linterp(fs_inst *inst, struct brw_reg dst, struct brw_reg *src) @@ -1949,12 +1915,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) generate_math_gen4(inst, dst, src[0]); } break; - case FS_OPCODE_PIXEL_X: - generate_pixel_xy(dst, true); - break; - case FS_OPCODE_PIXEL_Y: - generate_pixel_xy(dst, false); - break; case FS_OPCODE_CINTERP: brw_MOV(p, dst, src[0]); break; |