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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-07-31 08:36:35 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-08-10 12:04:04 -0700 |
| commit | 1bb339493cd892c8065266b93a296a84b1dfce9b (patch) | |
| tree | 32ca463fe39d78efab71a1383dccda033149aebe /src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | |
| parent | 0ac65abb466578aafbc753189cdc40fd9a6000b8 (diff) | |
| download | external_mesa3d-1bb339493cd892c8065266b93a296a84b1dfce9b.zip external_mesa3d-1bb339493cd892c8065266b93a296a84b1dfce9b.tar.gz external_mesa3d-1bb339493cd892c8065266b93a296a84b1dfce9b.tar.bz2 | |
i965/fs: Don't do redundant RA setup on IVB+
Acked-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 211f70e..b70895e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -79,6 +79,15 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) int base_reg_count = BRW_MAX_GRF; int index = (dispatch_width / 8) - 1; + if (dispatch_width > 8 && devinfo->gen >= 7) { + /* For IVB+, we don't need the PLN hacks or the even-reg alignment in + * SIMD16. Therefore, we can use the exact same register sets for + * SIMD16 as we do for SIMD8 and we don't need to recalculate them. + */ + compiler->fs_reg_sets[index] = compiler->fs_reg_sets[0]; + return; + } + /* The registers used to make up almost all values handled in the compiler * are a scalar value occupying a single register (or 2 registers in the * case of SIMD16, which is handled by dividing base_reg_count by 2 and |