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authorPaul Berry <stereotype441@gmail.com>2011-08-30 10:54:14 -0700
committerPaul Berry <stereotype441@gmail.com>2011-09-06 11:05:41 -0700
commit18dcda2dcff0ba49cf35656bb8936e3edd61c90d (patch)
tree7f0e1d522a8f24aeb4db6b66099ab07e869999c6 /src/mesa/drivers/dri/i965/brw_gs.c
parent78be5bcb222d379a07979de98ff5b9e3549de6a7 (diff)
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i965: GS: Use the VUE map to compute URB size.
The previous computation had two bugs: (a) it used a formula based on Gen5 for Gen6 and Gen7 as well. (b) it failed to account for the fact that PSIZ is stored in the VUE header. Fortunately, both bugs caused it to compute a URB size that was too large, which was benign. This patch computes the URB size directly from the VUE map, so it gets the result correct in all circumstances. Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_gs.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_gs.c23
1 files changed, 11 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index f4656af..ddeb5bf 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -62,17 +62,11 @@ static void compile_gs_prog( struct brw_context *brw,
memset(&c, 0, sizeof(c));
c.key = *key;
- /* Need to locate the two positions present in vertex + header.
- * These are currently hardcoded:
- */
- c.nr_attrs = brw_count_bits(c.key.attrs);
-
- if (intel->gen >= 5)
- c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
- else
- c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */
-
- c.nr_bytes = c.nr_regs * REG_SIZE;
+ /* The geometry shader needs to access the entire VUE. */
+ struct brw_vue_map vue_map;
+ brw_compute_vue_map(&vue_map, intel, c.key.nr_userclip,
+ c.key.do_twoside_color, c.key.attrs);
+ c.nr_regs = (vue_map.num_slots + 1)/2;
mem_ctx = NULL;
@@ -158,6 +152,7 @@ static void populate_key( struct brw_context *brw,
/* _NEW_LIGHT */
key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION);
+ key->do_twoside_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide);
if (key->primitive == GL_QUADS && ctx->Light.ShadeModel != GL_FLAT) {
/* Provide consistent primitive order with brw_set_prim's
* optimization of single quads to trifans.
@@ -165,6 +160,9 @@ static void populate_key( struct brw_context *brw,
key->pv_first = GL_TRUE;
}
+ /* _NEW_TRANSFORM */
+ key->nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled);
+
key->need_gs_prog = (intel->gen >= 6)
? 0
: (brw->primitive == GL_QUADS ||
@@ -198,7 +196,8 @@ static void prepare_gs_prog(struct brw_context *brw)
const struct brw_tracked_state brw_gs_prog = {
.dirty = {
- .mesa = _NEW_LIGHT,
+ .mesa = (_NEW_LIGHT |
+ _NEW_TRANSFORM),
.brw = BRW_NEW_PRIMITIVE,
.cache = CACHE_NEW_VS_PROG
},