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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-10-14 10:54:53 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-10-14 11:24:42 +0800 |
| commit | e8e79c1d7eed0f5ae8820611cb86bdbd6ce595e6 (patch) | |
| tree | a3483b9f1ee6f525ee55fad1a1374fa0099afd4b /src/mesa/drivers/dri/i965/brw_gs.h | |
| parent | a57ef244fc55476660f9fb76982130c5c0b25163 (diff) | |
| download | external_mesa3d-e8e79c1d7eed0f5ae8820611cb86bdbd6ce595e6.zip external_mesa3d-e8e79c1d7eed0f5ae8820611cb86bdbd6ce595e6.tar.gz external_mesa3d-e8e79c1d7eed0f5ae8820611cb86bdbd6ce595e6.tar.bz2 | |
i965: Fix GS hang on Sandybridge
Don't use r0 for FF_SYNC dest reg on Sandybridge, which would
smash FFID field in GS payload, that cause later URB write fail.
Also not use r0 in any URB write requiring allocate.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_gs.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index 813b8d4..7e35310 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -56,6 +56,7 @@ struct brw_gs_compile { struct { struct brw_reg R0; struct brw_reg vertex[MAX_GS_VERTS]; + struct brw_reg temp; } reg; /* 3 different ways of expressing vertex size: |