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| author | Xiang, Haihao <haihao.xiang@intel.com> | 2007-01-17 10:39:50 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2007-01-17 10:39:50 +0800 |
| commit | 747c9129c0b592941b14c290ff3d8ab22ad66acb (patch) | |
| tree | bbf80c50c3ddf49e3c345956556aeccc341412cc /src/mesa/drivers/dri/i965/brw_gs_emit.c | |
| parent | afba8f0d30974bf7fbb9533f23eb2f92d49ac526 (diff) | |
| download | external_mesa3d-747c9129c0b592941b14c290ff3d8ab22ad66acb.zip external_mesa3d-747c9129c0b592941b14c290ff3d8ab22ad66acb.tar.gz external_mesa3d-747c9129c0b592941b14c290ff3d8ab22ad66acb.tar.bz2 | |
I965: fix bug#9625-get the correct PV for quardstrip
The order of vertices in payload for quardstrip is (0, 1, 3, 2),
so the PV for quardstrip is c->reg.vertex[2].
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_gs_emit.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs_emit.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index e4eed36..9abb94d 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -116,6 +116,16 @@ void brw_gs_quads( struct brw_gs_compile *c ) brw_gs_emit_vue(c, c->reg.vertex[2], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); } +void brw_gs_quad_strip( struct brw_gs_compile *c ) +{ + brw_gs_alloc_regs(c, 4); + + brw_gs_emit_vue(c, c->reg.vertex[2], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); + brw_gs_emit_vue(c, c->reg.vertex[3], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); +} + void brw_gs_tris( struct brw_gs_compile *c ) { brw_gs_alloc_regs(c, 3); |