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| author | Eric Anholt <eric@anholt.net> | 2007-10-04 12:07:25 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2007-10-04 12:28:49 -0700 |
| commit | 77e0523fb7769df4bf43747e136b1653b2421b97 (patch) | |
| tree | 27337de5a5460aad8428969a504621c98e95fb16 /src/mesa/drivers/dri/i965/brw_gs_state.c | |
| parent | 0fc9efd8f0b1b6c4e3525a50e3478e5aef72531a (diff) | |
| download | external_mesa3d-77e0523fb7769df4bf43747e136b1653b2421b97.zip external_mesa3d-77e0523fb7769df4bf43747e136b1653b2421b97.tar.gz external_mesa3d-77e0523fb7769df4bf43747e136b1653b2421b97.tar.bz2 | |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_gs_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs_state.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c index 5826c01..5db4dd4 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_state.c +++ b/src/mesa/drivers/dri/i965/brw_gs_state.c @@ -46,7 +46,8 @@ static void upload_gs_unit( struct brw_context *brw ) /* CACHE_NEW_GS_PROG */ if (brw->gs.prog_active) { - gs.thread0.grf_reg_count = ((brw->gs.prog_data->total_grf-1) & ~15) / 16; + gs.thread0.grf_reg_count = + ALIGN(brw->gs.prog_data->total_grf, 16) / 16 - 1; gs.thread0.kernel_start_pointer = brw->gs.prog_gs_offset >> 6; gs.thread3.urb_entry_read_length = brw->gs.prog_data->urb_read_length; } |