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authorKenneth Graunke <kenneth@whitecape.org>2015-11-12 13:32:13 -0800
committerKenneth Graunke <kenneth@whitecape.org>2015-11-16 16:24:44 -0800
commit44d6c0c805d2911cc5dfe853e5bc5a505f87775f (patch)
tree1a6dc97e37963b7ceb973cc46a09fc1618f86dfc /src/mesa/drivers/dri/i965/brw_link.cpp
parenta2611ffe4b5f1852c59301f086b988233a1c62f3 (diff)
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i965: Convert scalar_* flags to a scalar_stage array.
I was going to add scalar_tcs and scalar_tes flags, and then thought better of it and decided to convert this to an array. Simpler. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_link.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_link.cpp11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
index 2991173..14421d4 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -66,12 +66,14 @@ brw_lower_packing_builtins(struct brw_context *brw,
gl_shader_stage shader_type,
exec_list *ir)
{
+ const struct brw_compiler *compiler = brw->intelScreen->compiler;
+
int ops = LOWER_PACK_SNORM_2x16
| LOWER_UNPACK_SNORM_2x16
| LOWER_PACK_UNORM_2x16
| LOWER_UNPACK_UNORM_2x16;
- if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
+ if (compiler->scalar_stage[shader_type]) {
ops |= LOWER_UNPACK_UNORM_4x8
| LOWER_UNPACK_SNORM_4x8
| LOWER_PACK_UNORM_4x8
@@ -84,7 +86,7 @@ brw_lower_packing_builtins(struct brw_context *brw,
* lowering is needed. For SOA code, the Half2x16 ops must be
* scalarized.
*/
- if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
+ if (compiler->scalar_stage[shader_type]) {
ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
| LOWER_UNPACK_HALF_2x16_TO_SPLIT;
}
@@ -103,6 +105,7 @@ process_glsl_ir(gl_shader_stage stage,
struct gl_shader *shader)
{
struct gl_context *ctx = &brw->ctx;
+ const struct brw_compiler *compiler = brw->intelScreen->compiler;
const struct gl_shader_compiler_options *options =
&ctx->Const.ShaderCompilerOptions[shader->Stage];
@@ -161,7 +164,7 @@ process_glsl_ir(gl_shader_stage stage,
do {
progress = false;
- if (is_scalar_shader_stage(brw->intelScreen->compiler, shader->Stage)) {
+ if (compiler->scalar_stage[shader->Stage]) {
brw_do_channel_expressions(shader->ir);
brw_do_vector_splitting(shader->ir);
}
@@ -252,7 +255,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
brw_add_texrect_params(prog);
prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
- is_scalar_shader_stage(compiler, stage));
+ compiler->scalar_stage[stage]);
_mesa_reference_program(ctx, &prog, NULL);
}