diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2014-09-03 14:28:59 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2014-09-04 23:06:27 -0700 |
| commit | 864c463485aafaa2802b18a7427f8b75dc96e3ef (patch) | |
| tree | a8b41434cd3b5b13fff67e85ae54c95fc5f7c62e /src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | |
| parent | 5d8f40a53a58c984906bc6509f01e31cc41ed1da (diff) | |
| download | external_mesa3d-864c463485aafaa2802b18a7427f8b75dc96e3ef.zip external_mesa3d-864c463485aafaa2802b18a7427f8b75dc96e3ef.tar.gz external_mesa3d-864c463485aafaa2802b18a7427f8b75dc96e3ef.tar.bz2 | |
Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404
Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
c5bdf9be1eca190417998d548fd140c1eca37a54
Conflicts:
src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
6f56e1424d923fd80c84090fbf4506c9eaaffea1
Conflicts:
src/mesa/drivers/dri/i965/brw_blorp.cpp
src/mesa/drivers/dri/i965/brw_state_cache.c
src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
88e3d404dad009d8cff5124cf8acee7daeaceb64
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_meta_fast_clear.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c index 7816140..168e5b1 100644 --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c @@ -376,7 +376,7 @@ set_fast_clear_op(struct brw_context *brw, uint32_t op) * 3DSTATE_PS. */ brw->wm.fast_clear_op = op; - SET_DIRTY_BIT(brw, BRW_NEW_FRAGMENT_PROGRAM); + brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; } static void @@ -400,8 +400,8 @@ use_rectlist(struct brw_context *brw, bool enable) * _NEW_BUFFERS to make sure we emit new SURFACE_STATE with the new fast * clear color value. */ - SET_DIRTY_BIT(mesa, _NEW_LIGHT | _NEW_BUFFERS); - SET_DIRTY_BIT(brw, BRW_NEW_FRAGMENT_PROGRAM); + brw->state.dirty.mesa |= _NEW_LIGHT | _NEW_BUFFERS; + brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; } bool @@ -602,7 +602,8 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb, * color before resolve and sets irb->mt->fast_clear_state to UNRESOLVED if * we render to it. */ - SET_DIRTY_BIT(mesa, _NEW_BUFFERS); + brw->state.dirty.mesa |= _NEW_BUFFERS; + /* Set the custom state back to normal and dirty the same bits as above */ use_rectlist(brw, false); |