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authorPaul Berry <stereotype441@gmail.com>2014-01-10 13:00:51 -0800
committerJordan Justen <jordan.l.justen@intel.com>2014-09-01 19:38:27 -0700
commit88e3d404dad009d8cff5124cf8acee7daeaceb64 (patch)
tree73b0ebeeefb8851e2810f123e04b28c805f05a63 /src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
parent94a909ec2df779bfdac6f42a25077b427b3873ea (diff)
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i965: Create a macro for setting a dirty bit.
This will make it easier to extend dirty bit handling to support compute shaders. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_meta_fast_clear.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_meta_fast_clear.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 168e5b1..7816140 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -376,7 +376,7 @@ set_fast_clear_op(struct brw_context *brw, uint32_t op)
* 3DSTATE_PS.
*/
brw->wm.fast_clear_op = op;
- brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
+ SET_DIRTY_BIT(brw, BRW_NEW_FRAGMENT_PROGRAM);
}
static void
@@ -400,8 +400,8 @@ use_rectlist(struct brw_context *brw, bool enable)
* _NEW_BUFFERS to make sure we emit new SURFACE_STATE with the new fast
* clear color value.
*/
- brw->state.dirty.mesa |= _NEW_LIGHT | _NEW_BUFFERS;
- brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
+ SET_DIRTY_BIT(mesa, _NEW_LIGHT | _NEW_BUFFERS);
+ SET_DIRTY_BIT(brw, BRW_NEW_FRAGMENT_PROGRAM);
}
bool
@@ -602,8 +602,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
* color before resolve and sets irb->mt->fast_clear_state to UNRESOLVED if
* we render to it.
*/
- brw->state.dirty.mesa |= _NEW_BUFFERS;
-
+ SET_DIRTY_BIT(mesa, _NEW_BUFFERS);
/* Set the custom state back to normal and dirty the same bits as above */
use_rectlist(brw, false);