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| author | Anuj Phogat <anuj.phogat@gmail.com> | 2015-08-18 15:47:13 -0700 |
|---|---|---|
| committer | Anuj Phogat <anuj.phogat@gmail.com> | 2015-09-28 12:43:43 -0700 |
| commit | 1dc41be9ebd07825836b0ca4b98e00ffc7ecc0ec (patch) | |
| tree | 0f792533704f12dada31f4d133bb200d79ecd990 /src/mesa/drivers/dri/i965/brw_misc_state.c | |
| parent | 21fdc59d349eb396b48f0919dfd1a8dc234b96b1 (diff) | |
| download | external_mesa3d-1dc41be9ebd07825836b0ca4b98e00ffc7ecc0ec.zip external_mesa3d-1dc41be9ebd07825836b0ca4b98e00ffc7ecc0ec.tar.gz external_mesa3d-1dc41be9ebd07825836b0ca4b98e00ffc7ecc0ec.tar.bz2 | |
i965: Use intel_get_tile_dims() to get tile masks
This will require change in the parameters passed to
intel_miptree_get_tile_masks().
V2: Rearrange the order of parameters. (Ben)
Change the name to intel_get_tile_masks(). (Topi)
V3: Use temporary variables in intel_get_tile_masks()
for clarity. Fix mask_y computation.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 2751152..7d17edb 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -174,13 +174,17 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt, uint32_t tile_mask_x = 0, tile_mask_y = 0; if (depth_mt) { - intel_miptree_get_tile_masks(depth_mt, &tile_mask_x, &tile_mask_y, false); + intel_get_tile_masks(depth_mt->tiling, depth_mt->tr_mode, + depth_mt->cpp, false, + &tile_mask_x, &tile_mask_y); if (intel_miptree_level_has_hiz(depth_mt, depth_level)) { uint32_t hiz_tile_mask_x, hiz_tile_mask_y; - intel_miptree_get_tile_masks(depth_mt->hiz_buf->mt, - &hiz_tile_mask_x, &hiz_tile_mask_y, - false); + intel_get_tile_masks(depth_mt->hiz_buf->mt->tiling, + depth_mt->hiz_buf->mt->tr_mode, + depth_mt->hiz_buf->mt->cpp, + false, &hiz_tile_mask_x, + &hiz_tile_mask_y); /* Each HiZ row represents 2 rows of pixels */ hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1; @@ -200,9 +204,11 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt, tile_mask_y |= 63; } else { uint32_t stencil_tile_mask_x, stencil_tile_mask_y; - intel_miptree_get_tile_masks(stencil_mt, - &stencil_tile_mask_x, - &stencil_tile_mask_y, false); + intel_get_tile_masks(stencil_mt->tiling, + stencil_mt->tr_mode, + stencil_mt->cpp, + false, &stencil_tile_mask_x, + &stencil_tile_mask_y); tile_mask_x |= stencil_tile_mask_x; tile_mask_y |= stencil_tile_mask_y; |