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authorChad Versace <chad.versace@linux.intel.com>2011-11-22 10:52:29 -0800
committerChad Versace <chad.versace@linux.intel.com>2011-11-22 10:52:29 -0800
commit4ce635c871d00e442efb2b265562685d7edd44ae (patch)
treeb20aebc5d0924a916b92b0b319dc3522fca06799 /src/mesa/drivers/dri/i965/brw_misc_state.c
parent1f3c5eae5c4be582e50c2d4d7950424d86059c45 (diff)
parente5411d8fdc6a7dda18d82746b84197ef83ee0a13 (diff)
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Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesa
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c22
1 files changed, 16 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 514c990..17da460 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -33,6 +33,7 @@
#include "intel_batchbuffer.h"
#include "intel_fbo.h"
+#include "intel_mipmap_tree.h"
#include "intel_regions.h"
#include "brw_context.h"
@@ -204,9 +205,15 @@ static void emit_depthbuffer(struct brw_context *brw)
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
- struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL;
+ struct intel_region *hiz_region = NULL;
unsigned int len;
+ if (depth_irb &&
+ depth_irb->mt &&
+ depth_irb->mt->hiz_mt) {
+ hiz_region = depth_irb->mt->hiz_mt->region;
+ }
+
/* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
* non-pipelined state that will need the PIPE_CONTROL workaround.
*/
@@ -272,6 +279,8 @@ static void emit_depthbuffer(struct brw_context *brw)
* [DevGT]: This field must be set to the same value (enabled or
* disabled) as Hierarchical Depth Buffer Enable
*/
+ struct intel_region *region = stencil_irb->mt->region;
+
assert(intel->has_separate_stencil);
assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
@@ -283,8 +292,8 @@ static void emit_depthbuffer(struct brw_context *brw)
(BRW_TILEWALK_YMAJOR << 26) |
(BRW_SURFACE_2D << 29));
OUT_BATCH(0);
- OUT_BATCH(((stencil_irb->region->width - 1) << 6) |
- (2 * stencil_irb->region->height - 1) << 19);
+ OUT_BATCH(((region->width - 1) << 6) |
+ (2 * region->height - 1) << 19);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -294,7 +303,7 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
} else {
- struct intel_region *region = depth_irb->region;
+ struct intel_region *region = depth_irb->mt->region;
unsigned int format;
uint32_t tile_x, tile_y, offset;
@@ -379,10 +388,11 @@ static void emit_depthbuffer(struct brw_context *brw)
/* Emit stencil buffer. */
if (stencil_irb) {
+ struct intel_region *region = stencil_irb->mt->region;
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
- OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1);
- OUT_RELOC(stencil_irb->region->bo,
+ OUT_BATCH(region->pitch * region->cpp - 1);
+ OUT_RELOC(region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();