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authorJuan A. Suarez Romero <jasuarez@igalia.com>2016-04-01 17:25:03 +0200
committerAlejandro PiƱeiro <apinheiro@igalia.com>2016-05-17 09:05:54 +0200
commitb0fb08e179d784ca319c3c547a874fd24ce93c3f (patch)
tree7ab4864f5d0cb57b7e94c8e77ea187fad16bbe7e /src/mesa/drivers/dri/i965/brw_nir.c
parent80535873bbed9d6fda7bb0d2cca3d0950afb8431 (diff)
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i965: take care of doubles when remapping VS attributes
Double-precision types require 1 slot in VUE for double and dvec2, and 2 slots for anything else. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_nir.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_nir.c26
1 files changed, 11 insertions, 15 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
index c501bc1..f37bf3a 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -96,7 +96,7 @@ add_const_offset_to_base(nir_shader *nir, nir_variable_mode mode)
}
static bool
-remap_vs_attrs(nir_block *block, GLbitfield64 inputs_read)
+remap_vs_attrs(nir_block *block, struct nir_shader_info *nir_info)
{
nir_foreach_instr(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
@@ -111,9 +111,11 @@ remap_vs_attrs(nir_block *block, GLbitfield64 inputs_read)
* before it and counting the bits.
*/
int attr = intrin->const_index[0];
- int slot = _mesa_bitcount_64(inputs_read & BITFIELD64_MASK(attr));
-
- intrin->const_index[0] = 4 * slot;
+ int slot = _mesa_bitcount_64(nir_info->inputs_read &
+ BITFIELD64_MASK(attr));
+ int dslot = _mesa_bitcount_64(nir_info->double_inputs_read &
+ BITFIELD64_MASK(attr));
+ intrin->const_index[0] = 4 * (slot + dslot);
}
}
return true;
@@ -199,9 +201,9 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
var->data.driver_location = var->data.location;
}
- /* Now use nir_lower_io to walk dereference chains. Attribute arrays
- * are loaded as one vec4 per element (or matrix column), so we use
- * type_size_vec4 here.
+ /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
+ * loaded as one vec4 or dvec4 per element (or matrix column), depending on
+ * whether it is a double-precision type or not.
*/
nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
@@ -214,18 +216,12 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
vs_attrib_wa_flags);
if (is_scalar) {
- /* Finally, translate VERT_ATTRIB_* values into the actual registers.
- *
- * Note that we can use nir->info.inputs_read instead of
- * key->inputs_read since the two are identical aside from Gen4-5
- * edge flag differences.
- */
- GLbitfield64 inputs_read = nir->info.inputs_read;
+ /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
nir_foreach_function(function, nir) {
if (function->impl) {
nir_foreach_block(block, function->impl) {
- remap_vs_attrs(block, inputs_read);
+ remap_vs_attrs(block, &nir->info);
}
}
}