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author | Chris Wilson <chris@chris-wilson.co.uk> | 2015-04-30 17:04:51 +0100 |
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committer | Kenneth Graunke <kenneth@whitecape.org> | 2015-06-24 10:35:04 -0700 |
commit | 4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9 (patch) | |
tree | 623f9d02e44c1601d8abf09fa89e7fd06186aa83 /src/mesa/drivers/dri/i965/brw_performance_monitor.c | |
parent | 9d4b9f1e0c661e5ed8ce2e71c76ce8cc1adf90dd (diff) | |
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i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_performance_monitor.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_performance_monitor.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c b/src/mesa/drivers/dri/i965/brw_performance_monitor.c index 2c8cd49..0a12375 100644 --- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c +++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c @@ -581,7 +581,7 @@ snapshot_statistics_registers(struct brw_context *brw, const int group = PIPELINE_STATS_COUNTERS; const int num_counters = ctx->PerfMonitor.Groups[group].NumCounters; - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); for (int i = 0; i < num_counters; i++) { if (BITSET_TEST(monitor->base.ActiveCounters[group], i)) { @@ -687,7 +687,7 @@ stop_oa_counters(struct brw_context *brw) * The amount of batch space it takes to emit an MI_REPORT_PERF_COUNT snapshot, * including the required PIPE_CONTROL flushes. * - * Sandybridge is the worst case scenario: intel_batchbuffer_emit_mi_flush + * Sandybridge is the worst case scenario: brw_emit_mi_flush * expands to three PIPE_CONTROLs which are 4 DWords each. We have to flush * before and after MI_REPORT_PERF_COUNT, so multiply by two. Finally, add * the 3 DWords for MI_REPORT_PERF_COUNT itself. @@ -713,7 +713,7 @@ emit_mi_report_perf_count(struct brw_context *brw, int batch_used = brw->batch.used; /* Reports apparently don't always get written unless we flush first. */ - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); if (brw->gen == 5) { /* Ironlake requires two MI_REPORT_PERF_COUNT commands to write all @@ -751,7 +751,7 @@ emit_mi_report_perf_count(struct brw_context *brw, } /* Reports apparently don't always get written unless we flush after. */ - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); (void) batch_used; assert(brw->batch.used - batch_used <= MI_REPORT_PERF_COUNT_BATCH_DWORDS * 4); |