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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2015-04-30 17:04:51 +0100 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2015-06-24 10:35:04 -0700 |
| commit | 4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9 (patch) | |
| tree | 623f9d02e44c1601d8abf09fa89e7fd06186aa83 /src/mesa/drivers/dri/i965/brw_pipe_control.c | |
| parent | 9d4b9f1e0c661e5ed8ce2e71c76ce8cc1adf90dd (diff) | |
| download | external_mesa3d-4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9.zip external_mesa3d-4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9.tar.gz external_mesa3d-4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9.tar.bz2 | |
i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_pipe_control.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index bd45a11..b4c86b9 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -189,7 +189,7 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, * already flushed (e.g., via a preceding MI_FLUSH). */ void -intel_emit_depth_stall_flushes(struct brw_context *brw) +brw_emit_depth_stall_flushes(struct brw_context *brw) { assert(brw->gen >= 6 && brw->gen <= 9); @@ -270,7 +270,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw) * really our business. That leaves only stall at scoreboard. */ void -intel_emit_post_sync_nonzero_flush(struct brw_context *brw) +brw_emit_post_sync_nonzero_flush(struct brw_context *brw) { brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | @@ -287,7 +287,7 @@ intel_emit_post_sync_nonzero_flush(struct brw_context *brw) * This is also used for the always_flush_cache driconf debug option. */ void -intel_batchbuffer_emit_mi_flush(struct brw_context *brw) +brw_emit_mi_flush(struct brw_context *brw) { if (brw->batch.ring == BLT_RING && brw->gen >= 6) { BEGIN_BATCH_BLT(4); @@ -321,7 +321,7 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw) * Flush Enable =1, a PIPE_CONTROL with any non-zero * post-sync-op is required. */ - intel_emit_post_sync_nonzero_flush(brw); + brw_emit_post_sync_nonzero_flush(brw); } } brw_emit_pipe_control_flush(brw, flags); |