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| author | Francisco Jerez <currojerez@riseup.net> | 2016-01-14 12:20:46 -0800 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2016-02-08 15:48:00 -0800 |
| commit | 53739fddc65a4cb34a2da14b873e95a451916267 (patch) | |
| tree | 579ddb9383b2602b25bee402eb0d8a9c336f88fb /src/mesa/drivers/dri/i965/brw_pipe_control.c | |
| parent | 10d84ba9f084174a1e8e7639dfb05dd855ba86e8 (diff) | |
| download | external_mesa3d-53739fddc65a4cb34a2da14b873e95a451916267.zip external_mesa3d-53739fddc65a4cb34a2da14b873e95a451916267.tar.gz external_mesa3d-53739fddc65a4cb34a2da14b873e95a451916267.tar.bz2 | |
i965: Rename define for the PIPE_CONTROL DC flush bit.
Its previous name was somewhat misleading, this really behaves like a
RW cache flush rather than an invalidation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_pipe_control.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 6c636d2..b41e28e 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -51,7 +51,7 @@ gen8_add_cs_stall_workaround_bits(uint32_t *flags) PIPE_CONTROL_WRITE_TIMESTAMP | PIPE_CONTROL_STALL_AT_SCOREBOARD | PIPE_CONTROL_DEPTH_STALL | - PIPE_CONTROL_DATA_CACHE_INVALIDATE; + PIPE_CONTROL_DATA_CACHE_FLUSH; /* If we're doing a CS stall, and don't already have one of the * workaround bits set, add "Stall at Pixel Scoreboard." |