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authorBen Widawsky <benjamin.widawsky@intel.com>2015-02-26 23:01:33 -0800
committerBen Widawsky <benjamin.widawsky@intel.com>2015-03-02 19:28:43 -0800
commit37c2687645bf44515dbd1bc1c066b02889ca46c4 (patch)
tree2b51591fb4219be3aca3b9911b9ffe8e4bcedb34 /src/mesa/drivers/dri/i965/brw_program.c
parente214000f258ae564e64d839cccee9418526f226b (diff)
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i965: Rename some PIPE_CONTROL flags
I'm not really sure of the origins of the existing flag names. Modern docs have some slightly different names. Having the correct names makes it easier to determine if existing PIPE_CONTROL flag settings are correct, as well as making adding new PIPE_CONTROLs easier. This originally came up while I was trying to implement workarounds and spotted some things called, "flush" which should have been called "invalidate." Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_program.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index aed595e..70b5a62 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -195,24 +195,24 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
bits |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
if (barriers & GL_UNIFORM_BARRIER_BIT)
- bits |= (PIPE_CONTROL_TC_FLUSH |
+ bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE);
if (barriers & GL_TEXTURE_FETCH_BARRIER_BIT)
- bits |= PIPE_CONTROL_TC_FLUSH;
+ bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
if (barriers & GL_TEXTURE_UPDATE_BARRIER_BIT)
- bits |= PIPE_CONTROL_WRITE_FLUSH;
+ bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
if (barriers & GL_FRAMEBUFFER_BARRIER_BIT)
bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_WRITE_FLUSH);
+ PIPE_CONTROL_RENDER_TARGET_FLUSH);
/* Typed surface messages are handled by the render cache on IVB, so we
* need to flush it too.
*/
if (brw->gen == 7 && !brw->is_haswell)
- bits |= PIPE_CONTROL_WRITE_FLUSH;
+ bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
brw_emit_pipe_control_flush(brw, bits);
}