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| author | Francisco Jerez <currojerez@riseup.net> | 2016-01-14 12:20:46 -0800 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2016-02-08 15:48:00 -0800 |
| commit | 53739fddc65a4cb34a2da14b873e95a451916267 (patch) | |
| tree | 579ddb9383b2602b25bee402eb0d8a9c336f88fb /src/mesa/drivers/dri/i965/brw_program.c | |
| parent | 10d84ba9f084174a1e8e7639dfb05dd855ba86e8 (diff) | |
| download | external_mesa3d-53739fddc65a4cb34a2da14b873e95a451916267.zip external_mesa3d-53739fddc65a4cb34a2da14b873e95a451916267.tar.gz external_mesa3d-53739fddc65a4cb34a2da14b873e95a451916267.tar.bz2 | |
i965: Rename define for the PIPE_CONTROL DC flush bit.
Its previous name was somewhat misleading, this really behaves like a
RW cache flush rather than an invalidation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_program.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_program.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 368efee..3112c0c 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -209,7 +209,7 @@ static void brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers) { struct brw_context *brw = brw_context(ctx); - unsigned bits = (PIPE_CONTROL_DATA_CACHE_INVALIDATE | + unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_CS_STALL); assert(brw->gen >= 7 && brw->gen <= 9); |