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author | Connor Abbott <cwabbott0@gmail.com> | 2015-06-06 10:55:21 -0400 |
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committer | Connor Abbott <cwabbott0@gmail.com> | 2015-10-30 02:19:24 -0400 |
commit | 45cd76e342d1e8ecea38e2048b96cf5be3a30fab (patch) | |
tree | e5a62c00c52b27d9dd7d21a55a2c25c72041f499 /src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | |
parent | 486268bdb03a36faf09d84e0458ff49dd1325c40 (diff) | |
download | external_mesa3d-45cd76e342d1e8ecea38e2048b96cf5be3a30fab.zip external_mesa3d-45cd76e342d1e8ecea38e2048b96cf5be3a30fab.tar.gz external_mesa3d-45cd76e342d1e8ecea38e2048b96cf5be3a30fab.tar.bz2 |
i965: dump scheduling cycle estimates
The heuristic we're using is rather lame, since it assumes everything is
non-uniform and loops execute 10 times, but it should be enough for
measuring improvements in the scheduler that don't result in a change in
the number of instructions.
v2:
- Switch loops and cycle counts to be compatible with older shader-db.
- Make loop heuristic 10x to match with spilling code.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index 094c47a..46da325 100644 --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp @@ -1467,6 +1467,24 @@ instruction_scheduler::schedule_instructions(bblock_t *block) if (block->end()->opcode == BRW_OPCODE_NOP) block->end()->remove(block); assert(instructions_to_schedule == 0); + + block->cycle_count = time; +} + +static unsigned get_cycle_count(cfg_t *cfg) +{ + unsigned count = 0, multiplier = 1; + foreach_block(block, cfg) { + if (block->start()->opcode == BRW_OPCODE_DO) + multiplier *= 10; /* assume that loops execute ~10 times */ + + count += block->cycle_count * multiplier; + + if (block->end()->opcode == BRW_OPCODE_WHILE) + multiplier /= 10; + } + + return count; } void @@ -1507,6 +1525,8 @@ instruction_scheduler::run(cfg_t *cfg) post_reg_alloc); bs->dump_instructions(); } + + cfg->cycle_count = get_cycle_count(cfg); } void |