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| author | Eric Anholt <eric@anholt.net> | 2013-11-04 22:56:33 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2013-11-12 15:05:07 -0800 |
| commit | 7c90947a0ba7f61b58a6fd5b94a08587e68d978e (patch) | |
| tree | 5178883aeb9b10e6608956e50cbc35360be6ea6e /src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | |
| parent | bc0e3bb4d05fbb5e8e2af8dce8170cb78cfe0e70 (diff) | |
| download | external_mesa3d-7c90947a0ba7f61b58a6fd5b94a08587e68d978e.zip external_mesa3d-7c90947a0ba7f61b58a6fd5b94a08587e68d978e.tar.gz external_mesa3d-7c90947a0ba7f61b58a6fd5b94a08587e68d978e.tar.bz2 | |
i965/fs: Fix message setup for SIMD8 spills.
In the SIMD16 spilling changes, I replaced a "1" in the spill path with
"mlen", but obviously it wasn't mlen before because spills have the g0
header along with the payload. The interface I was trying to use was
asking for how many physical regs we're writing, so we're looking for "1"
or "2".
I'm guessing this actually passed piglit because the high 8 bits of the
execution mask in SIMD8 mode are all 0s.
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp')
0 files changed, 0 insertions, 0 deletions