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| author | Matt Turner <mattst88@gmail.com> | 2014-03-08 11:07:10 -0800 |
|---|---|---|
| committer | Matt Turner <mattst88@gmail.com> | 2014-03-10 14:13:45 -0700 |
| commit | dafcc1b7c4bd23d9dad805d8ddd27c39c53e6a9f (patch) | |
| tree | b2b26081b9ab2b38257488b6c177c32dc112a0a4 /src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | |
| parent | 30259856a8a82a55c030df1ad052e505c61144bc (diff) | |
| download | external_mesa3d-dafcc1b7c4bd23d9dad805d8ddd27c39c53e6a9f.zip external_mesa3d-dafcc1b7c4bd23d9dad805d8ddd27c39c53e6a9f.tar.gz external_mesa3d-dafcc1b7c4bd23d9dad805d8ddd27c39c53e6a9f.tar.bz2 | |
i965: Disassemble 3-src operands widths' correctly.
<4,1,1> isn't a real thing. We meant <4,4,1>, i.e., each component of
the whole register.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index 32f30ba..5449c1b 100644 --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp @@ -132,20 +132,20 @@ schedule_node::set_latency_gen7(bool is_haswell) case BRW_OPCODE_MAD: /* 2 cycles * (since the last two src operands are in different register banks): - * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q }; + * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q }; * * 3 cycles on IVB, 4 on HSW * (since the last two src operands are in the same register bank): - * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q }; + * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q }; * * 18 cycles on IVB, 16 on HSW * (since the last two src operands are in different register banks): - * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q }; + * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q }; * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q }; * * 20 cycles on IVB, 18 on HSW * (since the last two src operands are in the same register bank): - * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q }; + * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q }; * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q }; */ @@ -158,20 +158,20 @@ schedule_node::set_latency_gen7(bool is_haswell) case BRW_OPCODE_LRP: /* 2 cycles * (since the last two src operands are in different register banks): - * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q }; + * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q }; * * 3 cycles on IVB, 4 on HSW * (since the last two src operands are in the same register bank): - * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q }; + * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q }; * * 16 cycles on IVB, 14 on HSW * (since the last two src operands are in different register banks): - * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q }; + * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q }; * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q }; * * 16 cycles * (since the last two src operands are in the same register bank): - * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q }; + * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q }; * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q }; */ |