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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-04-19 15:51:50 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-04-21 10:11:02 +0800 |
| commit | cdcef6cbf4dd80047819e9098e34a3b98bd502a4 (patch) | |
| tree | 712387517536e90d712c9851fc467ccbcf55a8ca /src/mesa/drivers/dri/i965/brw_sf_state.c | |
| parent | 9e258fc2bd6f2b9950606a0a92bb92c8959d9efd (diff) | |
| download | external_mesa3d-cdcef6cbf4dd80047819e9098e34a3b98bd502a4.zip external_mesa3d-cdcef6cbf4dd80047819e9098e34a3b98bd502a4.tar.gz external_mesa3d-cdcef6cbf4dd80047819e9098e34a3b98bd502a4.tar.bz2 | |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_sf_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_sf_state.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index 847c886..9712c31 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -177,7 +177,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key, sf.thread3.dispatch_grf_start_reg = 3; - if (intel->is_ironlake) + if (intel->gen == 5) sf.thread3.urb_entry_read_offset = 3; else sf.thread3.urb_entry_read_offset = 1; @@ -190,7 +190,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key, /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or * 48 (Ironlake) threads. */ - if (intel->is_ironlake) + if (intel->gen == 5) chipset_max_threads = 48; else chipset_max_threads = 24; |