summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_shader.cpp
diff options
context:
space:
mode:
authorJason Ekstrand <jason.ekstrand@intel.com>2016-08-22 15:01:08 -0700
committerJason Ekstrand <jason.ekstrand@intel.com>2016-09-03 08:23:06 -0700
commit527f37199929932300acc1688d8160e1f3b1d753 (patch)
tree8898917626d3a19f5a2c338e3320ab68150b70ff /src/mesa/drivers/dri/i965/brw_shader.cpp
parent55364ab5b7136e09a61d858f1167dee81e17bd9f (diff)
downloadexternal_mesa3d-527f37199929932300acc1688d8160e1f3b1d753.zip
external_mesa3d-527f37199929932300acc1688d8160e1f3b1d753.tar.gz
external_mesa3d-527f37199929932300acc1688d8160e1f3b1d753.tar.bz2
intel: s/brw_device_info/gen_device_info/
Generated by: sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_shader.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_shader.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index b1632a6..ea39252 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -147,7 +147,7 @@ brw_texture_offset(int *offsets, unsigned num_components)
}
const char *
-brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
+brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
{
switch (op) {
case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
@@ -777,7 +777,7 @@ backend_instruction::is_commutative() const
}
bool
-backend_instruction::is_3src(const struct brw_device_info *devinfo) const
+backend_instruction::is_3src(const struct gen_device_info *devinfo) const
{
return ::is_3src(devinfo, opcode);
}
@@ -959,7 +959,7 @@ backend_instruction::reads_accumulator_implicitly() const
}
bool
-backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
+backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
{
return writes_accumulator ||
(devinfo->gen < 6 &&
@@ -1154,7 +1154,7 @@ backend_shader::calculate_cfg()
*/
uint32_t
brw_assign_common_binding_table_offsets(gl_shader_stage stage,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
const struct gl_shader_program *shader_prog,
const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
@@ -1322,7 +1322,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
unsigned *final_assembly_size,
char **error_str)
{
- const struct brw_device_info *devinfo = compiler->devinfo;
+ const struct gen_device_info *devinfo = compiler->devinfo;
struct gl_linked_shader *shader =
shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];