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| author | Paul Berry <stereotype441@gmail.com> | 2014-01-10 13:00:51 -0800 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2014-09-01 19:38:27 -0700 |
| commit | 88e3d404dad009d8cff5124cf8acee7daeaceb64 (patch) | |
| tree | 73b0ebeeefb8851e2810f123e04b28c805f05a63 /src/mesa/drivers/dri/i965/brw_state_cache.c | |
| parent | 94a909ec2df779bfdac6f42a25077b427b3873ea (diff) | |
| download | external_mesa3d-88e3d404dad009d8cff5124cf8acee7daeaceb64.zip external_mesa3d-88e3d404dad009d8cff5124cf8acee7daeaceb64.tar.gz external_mesa3d-88e3d404dad009d8cff5124cf8acee7daeaceb64.tar.bz2 | |
i965: Create a macro for setting a dirty bit.
This will make it easier to extend dirty bit handling to support
compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_state_cache.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_cache.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index b0986ea..df2d806 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -158,7 +158,7 @@ brw_search_cache(struct brw_cache *cache, *(void **)out_aux = ((char *)item->key + item->key_size); if (item->offset != *inout_offset) { - brw->state.dirty.cache |= (1 << cache_id); + SET_DIRTY_BIT(cache, 1 << cache_id); *inout_offset = item->offset; } @@ -187,7 +187,7 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size) /* Since we have a new BO in place, we need to signal the units * that depend on it (state base address on gen5+, or unit state before). */ - brw->state.dirty.brw |= BRW_NEW_PROGRAM_CACHE; + SET_DIRTY_BIT(brw, BRW_NEW_PROGRAM_CACHE); } /** @@ -276,6 +276,7 @@ brw_upload_cache(struct brw_cache *cache, uint32_t *out_offset, void *out_aux) { + struct brw_context *brw = cache->brw; struct brw_cache_item *item = CALLOC_STRUCT(brw_cache_item); GLuint hash; void *tmp; @@ -320,7 +321,7 @@ brw_upload_cache(struct brw_cache *cache, *out_offset = item->offset; *(void **)out_aux = (void *)((char *)item->key + item->key_size); - cache->brw->state.dirty.cache |= 1 << cache_id; + SET_DIRTY_BIT(cache, 1 << cache_id); } void |