i965: Modify dirty bit handling to support 2 pipelines.

The hardware state for compute shaders is almost entirely orthogonal
to the hardware state for 3D rendering.  To avoid sending unnecessary
state to the hardware, we'll need to have a separate set of state
atoms for the compute pipeline and the 3D pipeline.  That means we
need to maintain two separate sets of dirty bits to determine which
state atoms need to be run.

But the dirty bits are not completely independent; for example, if
BRW_NEW_SURFACES is flagged while doing 3D rendering, then not only do
we need to re-run 3D state atoms that depend on BRW_NEW_SURFACES, but
we also need to re-run compute state atoms that depend on
BRW_NEW_SURFACES.  But we'll also need to re-run those state atoms the
next time the compute pipeline is run.

To accomplish this, we record two sets of dirty bits, one for each
pipeline.  When bits are dirtied (via SET_DIRTY_BIT() or
SET_DIRTY_ALL()) we set them to the dirty state in both pipelines.
When brw_state_upload() is run, we clear the dirty bits just for the
pipeline that was run.

Note that since the number of pipelines is known at compile time to be
2, the compiler should unroll the loops in SET_DIRTY_BIT() and
SET_DIRTY_ALL().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

1 files changed, 9 insertions, 5 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7324274..8e45f29 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -389,7 +389,8 @@ void brw_init_state( struct brw_context *brw )
    /* Make sure that brw->state.dirty.brw has enough bits to hold all possible
     * dirty flags.
     */
-   STATIC_ASSERT(BRW_NUM_STATE_BITS <= 8 * sizeof(brw->state.dirty.brw));
+   STATIC_ASSERT(BRW_NUM_STATE_BITS <=
+                 8 * sizeof(brw->state.pipeline_dirty[0].brw));
 
    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
    ctx->DriverFlags.NewTransformFeedbackProg = BRW_NEW_TRANSFORM_FEEDBACK;
@@ -565,13 +566,16 @@ brw_print_dirty_count(struct dirty_bit_map *bit_map)
 /***********************************************************************
  * Emit all state:
  */
-void brw_upload_state(struct brw_context *brw)
+void brw_upload_state(struct brw_context *brw, brw_pipeline pipeline)
 {
    struct gl_context *ctx = &brw->ctx;
-   struct brw_state_flags *state = &brw->state.dirty;
+   struct brw_state_flags *state = &brw->state.pipeline_dirty[pipeline];
    int i;
    static int dirty_count = 0;
 
+   assert(0 <= pipeline && pipeline < BRW_NUM_PIPELINES);
+   brw->state.current_pipeline = pipeline;
+
    SET_DIRTY_BIT(mesa, brw->NewGLState);
    brw->NewGLState = 0;
 
@@ -677,8 +681,8 @@ void brw_upload_state(struct brw_context *brw)
  * brw_upload_state() call.
  */
 void
-brw_clear_dirty_bits(struct brw_context *brw)
+brw_clear_dirty_bits(struct brw_context *brw, brw_pipeline pipeline)
 {
-   struct brw_state_flags *state = &brw->state.dirty;
+   struct brw_state_flags *state = &brw->state.pipeline_dirty[pipeline];
    memset(state, 0, sizeof(*state));
 }