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| author | Paul Berry <stereotype441@gmail.com> | 2014-01-10 14:23:52 -0800 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2014-09-01 19:38:27 -0700 |
| commit | 6f56e1424d923fd80c84090fbf4506c9eaaffea1 (patch) | |
| tree | 5a0b063ce27977487f95edd09c94eb0cb6fbddc6 /src/mesa/drivers/dri/i965/brw_state_upload.c | |
| parent | 88e3d404dad009d8cff5124cf8acee7daeaceb64 (diff) | |
| download | external_mesa3d-6f56e1424d923fd80c84090fbf4506c9eaaffea1.zip external_mesa3d-6f56e1424d923fd80c84090fbf4506c9eaaffea1.tar.gz external_mesa3d-6f56e1424d923fd80c84090fbf4506c9eaaffea1.tar.bz2 | |
i965: Create a macro for setting all dirty bits.
This will make it easier to extend dirty bit handling to support
compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_state_upload.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index b945e85..7324274 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -383,8 +383,8 @@ void brw_init_state( struct brw_context *brw ) brw_upload_initial_gpu_state(brw); - brw->state.dirty.mesa = ~0; - brw->state.dirty.brw = ~0; + SET_DIRTY_ALL(mesa); + SET_DIRTY_ALL(brw); /* Make sure that brw->state.dirty.brw has enough bits to hold all possible * dirty flags. |