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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-02-26 18:14:17 -0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-03-27 21:04:37 -0700 |
| commit | 9d32d358500733249d3c0264c7458c2e5a65f515 (patch) | |
| tree | 307b89a9a688b800258cc9295ac2b1196ddf6b8a /src/mesa/drivers/dri/i965/brw_state_upload.c | |
| parent | b2424fb0304cf4afd363b35c1dab49fb7edddb08 (diff) | |
| download | external_mesa3d-9d32d358500733249d3c0264c7458c2e5a65f515.zip external_mesa3d-9d32d358500733249d3c0264c7458c2e5a65f515.tar.gz external_mesa3d-9d32d358500733249d3c0264c7458c2e5a65f515.tar.bz2 | |
i965/skl: Disable partial resolve in VC
Recomendation [sic] is to set this field to 1 always. Programming it to default
value of 0, may have -ve impact on performance for MSAA WLs.
Another don't suck bit which needs to get set.
The patch wasn't as well tested as I would have liked, primarily I don't have
perf numbers for it, but it's getting to a point where it is in danger of being
lost.
v2: v1 was a mix of two patches. Since 0x7004 is masked, we only need to set it
once at initialization and make sure the pma workaround doesn't set the mask bit
(which it doesn't).
Move LRI to init gpu state (Ken)
Add a comment.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_state_upload.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 1b84859..e446de6 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -337,6 +337,16 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_upload_invariant_state(brw); + /* Recommended optimization for Victim Cache eviction in pixel backend. */ + if (brw->gen >= 9) { + BEGIN_BATCH(3); + OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); + OUT_BATCH(GEN7_CACHE_MODE_1); + OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) | + GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC); + ADVANCE_BATCH(); + } + if (brw->gen >= 8) { gen8_emit_3dstate_sample_pattern(brw); } |