i965: Handle mix-and-match TCS/TES with separate shader objects.

GL_ARB_separate_shader_objects allows the application to mix-and-match
TCS and TES programs separately.  This means that the interface between
the two stages isn't known until the final SSO pipeline is in place.

This isn't a great match for our hardware: the TCS and TES have to agree
on the Patch URB entry layout.  Since we store data as per-patch slots
followed by per-vertex slots, changing the number of per-patch slots can
significantly alter the layout.  This can easily happen with SSO.

To handle this, we store the [Patch]OutputsWritten and [Patch]InputsRead
bitfields in the TCS/TES program keys, introducing program recompiles.
brw_upload_programs() decides the layout for both TCS and TES, and
passes it to brw_upload_tcs/tes(), which store it in the key.

When creating the NIR for a shader specialization, we override
nir->info.inputs_read (and friends) to the program key's values.
Since everything uses those, no further compiler changes are needed.
This also replaces the hack in brw_create_nir().

To avoid recompiles, brw_precompile_tes() looks to see if there's a
TCS in the linked shader.  If so, it accounts for the TCS outputs,
just as brw_upload_programs() would.  This eliminates all recompiles
in the non-SSO case.  In the SSO case, there should only be recompiles
when using a TCS and TES that have different input/output interfaces.

Fixes Piglit's mix-and-match-tcs-tes test.

v2: Pull the brw_upload_programs code into a brw_upload_tess_programs()
    helper function (requested by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

1 files changed, 12 insertions, 1 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index ecb6fd0..2c925e7 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -67,6 +67,10 @@ brw_tcs_debug_recompile(struct brw_context *brw,
 
    found |= key_debug(brw, "input vertices", old_key->input_vertices,
                       key->input_vertices);
+   found |= key_debug(brw, "outputs written", old_key->outputs_written,
+                      key->outputs_written);
+   found |= key_debug(brw, "patch outputs written", old_key->patch_outputs_written,
+                      key->patch_outputs_written);
    found |= key_debug(brw, "TES primitive mode", old_key->tes_primitive_mode,
                       key->tes_primitive_mode);
    found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex);
@@ -224,7 +228,9 @@ brw_codegen_tcs_prog(struct brw_context *brw,
 
 
 void
-brw_upload_tcs_prog(struct brw_context *brw)
+brw_upload_tcs_prog(struct brw_context *brw,
+                    uint64_t per_vertex_slots,
+                    uint32_t per_patch_slots)
 {
    struct gl_context *ctx = &brw->ctx;
    struct gl_shader_program **current = ctx->_Shader->CurrentProgram;
@@ -248,6 +254,8 @@ brw_upload_tcs_prog(struct brw_context *brw)
    memset(&key, 0, sizeof(key));
 
    key.input_vertices = ctx->TessCtrlProgram.patch_vertices;
+   key.outputs_written = per_vertex_slots;
+   key.patch_outputs_written = per_patch_slots;
 
    /* We need to specialize our code generation for tessellation levels
     * based on the domain the DS is expecting to tessellate.
@@ -301,6 +309,9 @@ brw_tcs_precompile(struct gl_context *ctx,
 
    key.tes_primitive_mode = GL_TRIANGLES;
 
+   key.outputs_written = prog->OutputsWritten;
+   key.patch_outputs_written = prog->PatchOutputsWritten;
+
    success = brw_codegen_tcs_prog(brw, shader_prog, btcp, &key);
 
    brw->tcs.base.prog_offset = old_prog_offset;