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| author | Anuj Phogat <anuj.phogat@gmail.com> | 2015-04-14 22:06:47 -0700 |
|---|---|---|
| committer | Anuj Phogat <anuj.phogat@gmail.com> | 2015-06-08 13:57:11 -0700 |
| commit | 126078faca7a9da0f825d3ad07ce9b1183737240 (patch) | |
| tree | 2a6a7fb40240388ae0950f97c7bfe22cde44ea2f /src/mesa/drivers/dri/i965/brw_tex_layout.c | |
| parent | ef6b9985ea6b60a562daed3a9ed3be0f91f21e01 (diff) | |
| download | external_mesa3d-126078faca7a9da0f825d3ad07ce9b1183737240.zip external_mesa3d-126078faca7a9da0f825d3ad07ce9b1183737240.tar.gz external_mesa3d-126078faca7a9da0f825d3ad07ce9b1183737240.tar.bz2 | |
i965/gen9: Set tiled resource mode for the miptree
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_tex_layout.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index ec7c6c4..e461bfc 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -568,6 +568,8 @@ brw_miptree_layout(struct brw_context *brw, { bool gen6_hiz_or_stencil = false; + mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE; + if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) { const GLenum base_format = _mesa_get_format_base_format(mt->format); gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format); |