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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-03-16 16:06:10 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-03-22 16:46:15 -0700 |
| commit | 01425c45b32fa7f323515b05697c6cc0d245ad32 (patch) | |
| tree | b401b081ffebf0d8b1e2bb19a0786631e9f66a15 /src/mesa/drivers/dri/i965/brw_vec4.cpp | |
| parent | d7a25a9defe5fd42677266c0bcfd10909e5e49a4 (diff) | |
| download | external_mesa3d-01425c45b32fa7f323515b05697c6cc0d245ad32.zip external_mesa3d-01425c45b32fa7f323515b05697c6cc0d245ad32.tar.gz external_mesa3d-01425c45b32fa7f323515b05697c6cc0d245ad32.tar.bz2 | |
i965: Remove the RCP+RSQ algebraic optimizations
NIR already has this optimization and it can do much better than the little
peephole in the backend.
No shader-db change on Haswell or Broadwell.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.cpp | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index baf72a2..b9cf3f6 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -699,17 +699,6 @@ vec4_visitor::opt_algebraic() break; } break; - case SHADER_OPCODE_RCP: { - vec4_instruction *prev = (vec4_instruction *)inst->prev; - if (prev->opcode == SHADER_OPCODE_SQRT) { - if (inst->src[0].equals(src_reg(prev->dst))) { - inst->opcode = SHADER_OPCODE_RSQ; - inst->src[0] = prev->src[0]; - progress = true; - } - } - break; - } case SHADER_OPCODE_BROADCAST: if (is_uniform(inst->src[0]) || inst->src[1].is_zero()) { |