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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-04-05 14:06:10 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-04-15 14:04:37 -0700 |
| commit | 75b68f9114dc3ba1b501fb7de8198c03b3dcb1fd (patch) | |
| tree | 544c063ae3711cc50ca9ab8f9fd86892da67de88 /src/mesa/drivers/dri/i965/brw_vec4.cpp | |
| parent | 4a80890177015fef792ac2e069452fe340f36769 (diff) | |
| download | external_mesa3d-75b68f9114dc3ba1b501fb7de8198c03b3dcb1fd.zip external_mesa3d-75b68f9114dc3ba1b501fb7de8198c03b3dcb1fd.tar.gz external_mesa3d-75b68f9114dc3ba1b501fb7de8198c03b3dcb1fd.tar.bz2 | |
i965/vec4: Move can_do_writemask to vec4_instruction
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.cpp | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 0025343..4d0efa8 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -239,6 +239,34 @@ vec4_instruction::can_do_source_mods(const struct brw_device_info *devinfo) } bool +vec4_instruction::can_do_writemask(const struct brw_device_info *devinfo) +{ + switch (opcode) { + case SHADER_OPCODE_GEN4_SCRATCH_READ: + case VS_OPCODE_PULL_CONSTANT_LOAD: + case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: + case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9: + case TCS_OPCODE_SET_INPUT_URB_OFFSETS: + case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: + case TES_OPCODE_CREATE_INPUT_READ_HEADER: + case TES_OPCODE_ADD_INDIRECT_URB_OFFSET: + case VEC4_OPCODE_URB_READ: + return false; + default: + /* The MATH instruction on Gen6 only executes in align1 mode, which does + * not support writemasking. + */ + if (devinfo->gen == 6 && is_math()) + return false; + + if (is_tex()) + return false; + + return true; + } +} + +bool vec4_instruction::can_change_types() const { return dst.type == src[0].type && |