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| author | Kenneth Graunke <kenneth@whitecape.org> | 2016-01-05 01:53:57 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2016-02-09 14:54:26 -0800 |
| commit | 830b075e86e3e9af1bf12316d0f9d888a85a973b (patch) | |
| tree | 409955666698a2186cc17c4a80065902957580bb /src/mesa/drivers/dri/i965/brw_vec4.cpp | |
| parent | 8b0fb1c152fe191768953aa8c77b89034a377f83 (diff) | |
| download | external_mesa3d-830b075e86e3e9af1bf12316d0f9d888a85a973b.zip external_mesa3d-830b075e86e3e9af1bf12316d0f9d888a85a973b.tar.gz external_mesa3d-830b075e86e3e9af1bf12316d0f9d888a85a973b.tar.bz2 | |
i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.
Bit 0 of the Patch Header is "TR DS Cache Disable". Setting that bit
disables the DS Cache for tessellator-output topologies resulting in
stitch-transition regions (but leaves it enabled for other cases).
We probably shouldn't leave this to chance - the URB could contain
garbage - which could result in the cache randomly being turned on
or off.
This patch makes the final EOT write 0 to the first DWord (which
only contains this one bit). This ensures the cache is always on.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index e7aec1f..e8bc2ec 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -274,9 +274,9 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst) case SHADER_OPCODE_INT_QUOTIENT: case SHADER_OPCODE_INT_REMAINDER: case SHADER_OPCODE_POW: + case TCS_OPCODE_THREAD_END: return 2; case VS_OPCODE_URB_WRITE: - case TCS_OPCODE_THREAD_END: return 1; case VS_OPCODE_PULL_CONSTANT_LOAD: return 2; |