summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
diff options
context:
space:
mode:
authorFrancisco Jerez <currojerez@riseup.net>2016-09-01 16:55:46 -0700
committerFrancisco Jerez <currojerez@riseup.net>2016-09-14 14:50:53 -0700
commitd28cfa35fec75c367b940ff829ba8eaa035fbd22 (patch)
treeefdc81a8baa05246ca5d9b76c8e295aa4c43c63c /src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
parentc458eeb94620fbce0a37474fc292545002d67f76 (diff)
downloadexternal_mesa3d-d28cfa35fec75c367b940ff829ba8eaa035fbd22.zip
external_mesa3d-d28cfa35fec75c367b940ff829ba8eaa035fbd22.tar.gz
external_mesa3d-d28cfa35fec75c367b940ff829ba8eaa035fbd22.tar.bz2
i965/vec4: Add wrapper functions for vec4_instruction::regs_read and ::regs_written.
This is in preparation for dropping vec4_instruction::regs_read and ::regs_written in favor of more accurate alternatives expressed in byte units. The main reason these wrappers are useful is that a number of optimization passes implement dataflow analysis with register granularity, so these helpers will come in handy once we've switched register offsets and sizes to the byte representation. The wrapper functions will also make sure that GRF misalignment (currently neglected by most of the back-end) is taken into account correctly in the calculation of regs_read and regs_written. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_cse.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_cse.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
index 10898a5..f0908b9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
@@ -178,10 +178,10 @@ vec4_visitor::opt_cse_local(bblock_t *block)
bool no_existing_temp = entry->tmp.file == BAD_FILE;
if (no_existing_temp && !entry->generator->dst.is_null()) {
entry->tmp = retype(src_reg(VGRF, alloc.allocate(
- entry->generator->regs_written),
+ regs_written(entry->generator)),
NULL), inst->dst.type);
- for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
+ for (unsigned i = 0; i < regs_written(entry->generator); ++i) {
vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
offset(entry->tmp, i));
copy->force_writemask_all =
@@ -196,7 +196,7 @@ vec4_visitor::opt_cse_local(bblock_t *block)
if (!inst->dst.is_null()) {
assert(inst->dst.type == entry->tmp.type);
- for (unsigned i = 0; i < inst->regs_written; ++i) {
+ for (unsigned i = 0; i < regs_written(inst); ++i) {
vec4_instruction *copy = MOV(offset(inst->dst, i),
offset(entry->tmp, i));
copy->force_writemask_all = inst->force_writemask_all;