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author | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-04-15 18:00:05 -0700 |
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committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-04-22 16:00:34 -0700 |
commit | 28e9601d0e681411b60a7de8be9f401b0df77d29 (patch) | |
tree | b047241dc1652427e349488899f44fb3345eaa5e /src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp | |
parent | 73bf8f3d6b6b571175c5ce324b44fef26915875f (diff) | |
download | external_mesa3d-28e9601d0e681411b60a7de8be9f401b0df77d29.zip external_mesa3d-28e9601d0e681411b60a7de8be9f401b0df77d29.tar.gz external_mesa3d-28e9601d0e681411b60a7de8be9f401b0df77d29.tar.bz2 |
i965: Add a devinfo field to backend_visitor and use it for gen checks
Reviewed-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp index 70d2af5..8fc7a36 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp @@ -37,7 +37,7 @@ using namespace brw; static bool -can_do_writemask(const struct brw_context *brw, +can_do_writemask(const struct brw_device_info *devinfo, const vec4_instruction *inst) { switch (inst->opcode) { @@ -50,7 +50,7 @@ can_do_writemask(const struct brw_context *brw, /* The MATH instruction on Gen6 only executes in align1 mode, which does * not support writemasking. */ - if (brw->gen == 6 && inst->is_math()) + if (devinfo->gen == 6 && inst->is_math()) return false; if (inst->is_tex()) @@ -90,7 +90,7 @@ vec4_visitor::dead_code_eliminate() /* If the instruction can't do writemasking, then it's all or * nothing. */ - if (!can_do_writemask(brw, inst)) { + if (!can_do_writemask(devinfo, inst)) { bool result = result_live[0] | result_live[1] | result_live[2] | result_live[3]; result_live[0] = result; |