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author | Kenneth Graunke <kenneth@whitecape.org> | 2016-02-24 23:43:17 -0800 |
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committer | Kenneth Graunke <kenneth@whitecape.org> | 2016-02-26 15:55:59 -0800 |
commit | 8151003ade952c3e9d8284fada9237e1311cf173 (patch) | |
tree | 8523270dd43472e4f0ef08cb1a548e0e12013acb /src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | |
parent | 15b3639bf1b0676e74b107d74653185eedbc6688 (diff) | |
download | external_mesa3d-8151003ade952c3e9d8284fada9237e1311cf173.zip external_mesa3d-8151003ade952c3e9d8284fada9237e1311cf173.tar.gz external_mesa3d-8151003ade952c3e9d8284fada9237e1311cf173.tar.bz2 |
i965: Avoid recalculating the normal VUE map for IO lowering.
The caller already computes it. Now that we have stage specific
functions, it's really easy to pass this in.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 37 |
1 files changed, 19 insertions, 18 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp index 7f59db4..7df6c72 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp @@ -596,9 +596,27 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, const bool is_scalar = compiler->scalar_stage[MESA_SHADER_GEOMETRY]; nir_shader *shader = nir_shader_clone(mem_ctx, src_shader); + + /* The GLSL linker will have already matched up GS inputs and the outputs + * of prior stages. The driver does extend VS outputs in some cases, but + * only for legacy OpenGL or Gen4-5 hardware, neither of which offer + * geometry shader support. So we can safely ignore that. + * + * For SSO pipelines, we use a fixed VUE map layout based on variable + * locations, so we can rely on rendezvous-by-location making this work. + * + * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not + * written by previous stages and shows up via payload magic. + */ + GLbitfield64 inputs_read = + shader->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID; + brw_compute_vue_map(compiler->devinfo, + &c.input_vue_map, inputs_read, + shader->info.separate_shader); + shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex, is_scalar); - brw_nir_lower_vue_inputs(shader, compiler->devinfo, is_scalar); + brw_nir_lower_vue_inputs(shader, is_scalar, &c.input_vue_map); brw_nir_lower_vue_outputs(shader, is_scalar); shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar); @@ -777,23 +795,6 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, prog_data->vertices_in = shader->info.gs.vertices_in; - /* The GLSL linker will have already matched up GS inputs and the outputs - * of prior stages. The driver does extend VS outputs in some cases, but - * only for legacy OpenGL or Gen4-5 hardware, neither of which offer - * geometry shader support. So we can safely ignore that. - * - * For SSO pipelines, we use a fixed VUE map layout based on variable - * locations, so we can rely on rendezvous-by-location making this work. - * - * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not - * written by previous stages and shows up via payload magic. - */ - GLbitfield64 inputs_read = - shader->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID; - brw_compute_vue_map(compiler->devinfo, - &c.input_vue_map, inputs_read, - shader->info.separate_shader); - /* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we * need to program a URB read length of ceiling(num_slots / 2). */ |