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author | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-11-25 09:36:34 -0800 |
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committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-04-14 15:59:33 -0700 |
commit | 056849772f66582fd7e8a181c3fb16955f84243b (patch) | |
tree | 336ddd4e9437b21f68b7a3a2395c7e85c97d7bc0 /src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | |
parent | 479e38ad63ab1421afe4f25d36f434ac2e12e817 (diff) | |
download | external_mesa3d-056849772f66582fd7e8a181c3fb16955f84243b.zip external_mesa3d-056849772f66582fd7e8a181c3fb16955f84243b.tar.gz external_mesa3d-056849772f66582fd7e8a181c3fb16955f84243b.tar.bz2 |
i965/vec4: Use MOV_INDIRECT instead of reladdr for indirect push constants
This commit moves us to an instruction based model rather than a
register-based model for indirects. This is more accurate anyway as we
have to emit instructions to resolve the reladdr. It's also a lot simpler
because it gets rid of the recursive reladdr problem by design.
One side-effect of this is that we need a whole new algorithm in
move_uniform_array_access_to_pull_constants. This new algorithm is much
more straightforward than the old one and is fairly similar to what we're
already doing in the FS backend.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_nir.cpp')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 80845dc..3259c8f 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp @@ -708,12 +708,14 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) /* Offsets are in bytes but they should always be multiples of 16 */ assert(const_offset->u32[0] % 16 == 0); src.reg_offset = const_offset->u32[0] / 16; + + emit(MOV(dest, src)); } else { - src_reg tmp = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1); - src.reladdr = new(mem_ctx) src_reg(tmp); - } + src_reg indirect = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1); - emit(MOV(dest, src)); + emit(SHADER_OPCODE_MOV_INDIRECT, dest, src, + indirect, brw_imm_ud(instr->const_index[1])); + } break; } |