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| author | Matt Turner <mattst88@gmail.com> | 2015-11-02 12:12:44 -0800 |
|---|---|---|
| committer | Matt Turner <mattst88@gmail.com> | 2015-11-19 11:12:24 -0800 |
| commit | f9a9ba5eac2f1934bd7fecc92cd309f22411164b (patch) | |
| tree | 9bca94feec1b253d8810400c9d6798b436512bc3 /src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp | |
| parent | 9b978046eb1d1657060365e8dcde4aad41b50af9 (diff) | |
| download | external_mesa3d-f9a9ba5eac2f1934bd7fecc92cd309f22411164b.zip external_mesa3d-f9a9ba5eac2f1934bd7fecc92cd309f22411164b.tar.gz external_mesa3d-f9a9ba5eac2f1934bd7fecc92cd309f22411164b.tar.bz2 | |
i965/vec4: Replace src_reg(imm) constructors with brw_imm_*().
Cuts 1.5k of .text.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp b/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp index a7c286d..28002c5 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp @@ -71,7 +71,7 @@ namespace { bld.MOV(writemask(tmp, mask), src); if (n < 4) - bld.MOV(writemask(tmp, ~mask), 0); + bld.MOV(writemask(tmp, ~mask), brw_imm_d(0)); return emit_stride(bld, src_reg(tmp), n, has_simd4x2 ? 1 : 4, 1); } @@ -143,7 +143,7 @@ namespace brw { /* Emit the message send instruction. */ const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, ret_sz); vec4_instruction *inst = - bld.emit(op, dst, src_reg(payload), usurface, arg); + bld.emit(op, dst, src_reg(payload), usurface, brw_imm_ud(arg)); inst->mlen = sz; inst->regs_written = ret_sz; inst->header_size = header_sz; @@ -235,7 +235,7 @@ namespace brw { const vec4_builder ubld = bld.exec_all(); const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD); - ubld.MOV(dst, src_reg(0)); + ubld.MOV(dst, brw_imm_d(0)); if (bld.shader->devinfo->gen == 7 && !bld.shader->devinfo->is_haswell) { @@ -243,7 +243,7 @@ namespace brw { * have no SIMD4x2 variant. We only use the two X channels * in that case, mask everything else out. */ - ubld.MOV(writemask(dst, WRITEMASK_W), src_reg(0x11)); + ubld.MOV(writemask(dst, WRITEMASK_W), brw_imm_d(0x11)); } return src_reg(dst); |