i965: Don't set interleave or complete on TCS EOT message.

Setting interleave on the TCS EOT message causes Ivybridge hardware to
GPU hang like crazy.  Individual tests would pass, but running even a
simple test like nop.shader_test in a loop would hang within 1-3 runs.
Adding sleep delays worked around the problem, somehow.

Interleave doesn't make much sense given that we only have one patch
URB handle, not two.  Complete doesn't seem useful either.

There's no reason to actually set those bits.  We were just being lazy.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
index 7693f09..fb6ca8e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
@@ -203,9 +203,9 @@ vec4_tcs_visitor::emit_thread_end()
    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
       emit_shader_time_end();
 
-   inst = emit(VS_OPCODE_URB_WRITE);
-   inst->mlen = 1;   /* just the header, no data. */
-   inst->urb_write_flags = BRW_URB_WRITE_EOT_COMPLETE;
+   inst = emit(TCS_OPCODE_THREAD_END);
+   inst->base_mrf = 14;
+   inst->mlen = 1;
 }