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author | Paul Berry <stereotype441@gmail.com> | 2011-09-27 12:57:08 -0700 |
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committer | Paul Berry <stereotype441@gmail.com> | 2011-10-06 19:29:14 -0700 |
commit | 018ea68d8780ab5baeef0b8122b8410e5e55ae6d (patch) | |
tree | fac8a7a1bcc65420a1d29edf418124753348d124 /src/mesa/drivers/dri/i965/brw_vs_emit.c | |
parent | f4f686e825ad2d64e50fb9e2491ef60507d59c38 (diff) | |
download | external_mesa3d-018ea68d8780ab5baeef0b8122b8410e5e55ae6d.zip external_mesa3d-018ea68d8780ab5baeef0b8122b8410e5e55ae6d.tar.gz external_mesa3d-018ea68d8780ab5baeef0b8122b8410e5e55ae6d.tar.bz2 |
i965 Gen6+: De-compact clip planes.
Previously, if the user enabled a non-consecutive set of clip planes
(e.g. 0, 1, and 3), the driver would compact them down to a
consecutive set starting at 0. This optimization was of dubious
value, and complicated the implementation of gl_ClipDistance.
This patch changes the driver so that with Gen6 and later chipsets, we
no longer compact the clip planes. However, we still discard any clip
planes beyond the highest number that is in use, so performance should
not be affected for applications that use clip planes consecutively
from 0.
With chipsets previous to Gen6, we still compact the clip planes,
since the pre-Gen6 clipper thread relies on this behavior.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vs_emit.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs_emit.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 8845580..7326b3a 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -204,17 +204,17 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) */ if (c->key.userclip_active) { if (intel->gen >= 6) { - for (i = 0; i < c->key.nr_userclip_planes; i++) { + for (i = 0; i <= c->key.nr_userclip_plane_consts; i++) { c->userplane[i] = stride(brw_vec4_grf(reg + i / 2, (i % 2) * 4), 0, 4, 1); } - reg += ALIGN(c->key.nr_userclip_planes, 2) / 2; + reg += ALIGN(c->key.nr_userclip_plane_consts, 2) / 2; } else { - for (i = 0; i < c->key.nr_userclip_planes; i++) { + for (i = 0; i < c->key.nr_userclip_plane_consts; i++) { c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2, (i % 2) * 4), 0, 4, 1); } - reg += (ALIGN(6 + c->key.nr_userclip_planes, 4) / 4) * 2; + reg += (ALIGN(6 + c->key.nr_userclip_plane_consts, 4) / 4) * 2; } } @@ -239,7 +239,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) */ if (intel->gen >= 6) { /* We can only load 32 regs of push constants. */ - max_constant = 32 * 2 - c->key.nr_userclip_planes; + max_constant = 32 * 2 - c->key.nr_userclip_plane_consts; } else { max_constant = BRW_MAX_GRF - 20 - c->vp->program.Base.NumTemporaries; } @@ -1565,7 +1565,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) /* Set the user clip distances in dword 8-15. (m3-4)*/ if (c->key.userclip_active) { - for (i = 0; i < c->key.nr_userclip_planes; i++) { + for (i = 0; i < c->key.nr_userclip_plane_consts; i++) { struct brw_reg m; if (i < 4) m = brw_message_reg(3); @@ -1593,7 +1593,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) header1, brw_imm_ud(0x7ff<<8)); } - for (i = 0; i < c->key.nr_userclip_planes; i++) { + for (i = 0; i < c->key.nr_userclip_plane_consts; i++) { brw_set_conditionalmod(p, BRW_CONDITIONAL_L); brw_DP4(p, brw_null_reg(), pos, c->userplane[i]); brw_OR(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(1<<i)); |