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author | Eric Anholt <eric@anholt.net> | 2013-03-14 14:41:37 -0700 |
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committer | Eric Anholt <eric@anholt.net> | 2013-04-01 16:17:25 -0700 |
commit | 740350c982bd2735b9eb9063c2b91856b6f1ad31 (patch) | |
tree | 4304356b9eefd81c2ab17382a022fb2290cea684 /src/mesa/drivers/dri/i965/brw_vs_surface_state.c | |
parent | 2f41a601455e6e0366e28b6b84871842cb4bd341 (diff) | |
download | external_mesa3d-740350c982bd2735b9eb9063c2b91856b6f1ad31.zip external_mesa3d-740350c982bd2735b9eb9063c2b91856b6f1ad31.tar.gz external_mesa3d-740350c982bd2735b9eb9063c2b91856b6f1ad31.tar.bz2 |
i965: Make the fragment shader pull constants index by dwords, not vec4s.
We want to load vec4s, since loading a vec4 instead of a dword is
basically no increased latency. But for variable indexed access, the
previous requirement of aligned vec4s for a sampler LD was hard to
implement.
Note that this change only affects those messages that use the surface
format, like sampler LDs, but not to the untyped data cache loads we've
used in other cases.
No significant performance difference on my GLSL demo with uniforms forced
to take the varying pull constants path (n=4).
NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vs_surface_state.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index 6c0b690..675a84c 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -91,7 +91,7 @@ brw_upload_vs_pull_constants(struct brw_context *brw) const int surf = SURF_INDEX_VERT_CONST_BUFFER; intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size, - &brw->vs.surf_offset[surf]); + &brw->vs.surf_offset[surf], false); brw->state.dirty.brw |= BRW_NEW_VS_CONSTBUF; } |