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| author | Kenneth Graunke <kenneth@whitecape.org> | 2011-11-01 10:54:08 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2011-11-10 22:51:19 -0800 |
| commit | 6ba9090ea05e817bd38c1fcc63c53168b16593c7 (patch) | |
| tree | fefb9ecff7cd5ef9227228fae00bb664fc86acdc /src/mesa/drivers/dri/i965/brw_wm_state.c | |
| parent | 0983c6869bead0c31c62e5b1dda7f70898d43971 (diff) | |
| download | external_mesa3d-6ba9090ea05e817bd38c1fcc63c53168b16593c7.zip external_mesa3d-6ba9090ea05e817bd38c1fcc63c53168b16593c7.tar.gz external_mesa3d-6ba9090ea05e817bd38c1fcc63c53168b16593c7.tar.bz2 | |
i965: Use 0 for the number of binding table entries in 3DSTATE_(VS|WM).
These fields control how many entries the hardware prefetches into the
state cache, so they only impact performance, not correctness. However,
it's not clear how to use this in a way that's beneficial.
According to the documentation, kernels "using a large number" of
entries may wish to program this to zero to avoid thrashing the cache;
it's unclear how many is too many. Also, Ironlake's WM was missing this
feature entirely---the count had to be zero.
The dirty bit tracking to handle this complicates the surface state
and binding table setup; removing it should simplify things and make
future refactoring easier. So just set 0 for the number of entries
rather than trying to compute and track it.
Appears to have no impact on Nexuiz and OpenArena on Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_state.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 51ef745..69d7a76 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -113,12 +113,7 @@ brw_upload_wm_unit(struct brw_context *brw) wm->thread1.depth_coef_urb_read_offset = 1; wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; - if (intel->gen == 5) - wm->thread1.binding_table_entry_count = 0; /* hardware requirement */ - else { - /* BRW_NEW_NR_SURFACES */ - wm->thread1.binding_table_entry_count = brw->wm.nr_surfaces; - } + wm->thread1.binding_table_entry_count = 0; if (brw->wm.prog_data->total_scratch != 0) { wm->thread2.scratch_space_base_pointer = @@ -263,8 +258,7 @@ const struct brw_tracked_state brw_wm_unit = { .brw = (BRW_NEW_BATCH | BRW_NEW_PROGRAM_CACHE | BRW_NEW_FRAGMENT_PROGRAM | - BRW_NEW_CURBE_OFFSETS | - BRW_NEW_NR_WM_SURFACES), + BRW_NEW_CURBE_OFFSETS), .cache = (CACHE_NEW_WM_PROG | CACHE_NEW_SAMPLER) |