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| author | Chris Forbes <chrisf@ijw.co.nz> | 2013-06-10 08:01:41 +1200 |
|---|---|---|
| committer | Chris Forbes <chrisf@ijw.co.nz> | 2013-07-14 19:58:25 +1200 |
| commit | b616d0166158872a135153e27c391424fe655117 (patch) | |
| tree | 2d012e435510c8d985111369169f829766383771 /src/mesa/drivers/dri/i965/brw_wm_state.c | |
| parent | 1ec66f2fb2fea0497efebc1db83c75ec95a816a4 (diff) | |
| download | external_mesa3d-b616d0166158872a135153e27c391424fe655117.zip external_mesa3d-b616d0166158872a135153e27c391424fe655117.tar.gz external_mesa3d-b616d0166158872a135153e27c391424fe655117.tar.bz2 | |
i965: Gen4/5: use IEEE floating point mode for GLSL shaders.
Fixes isinf(), isnan() from GLSL 1.30
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_state.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index f221846..631f351 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -110,7 +110,15 @@ brw_upload_wm_unit(struct brw_context *brw) (wm->wm9.grf_reg_count_2 << 1)) >> 6; wm->thread1.depth_coef_urb_read_offset = 1; - wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; + /* Use ALT floating point mode for ARB fragment programs, because they + * require 0^0 == 1. Even though _CurrentFragmentProgram is used for + * rendering, CurrentFragmentProgram is used for this check to + * differentiate between the GLSL and non-GLSL cases. + */ + if (ctx->Shader.CurrentFragmentProgram == NULL) + wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; + else + wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754; wm->thread1.binding_table_entry_count = 0; |