diff options
author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-04-28 15:37:39 -0700 |
---|---|---|
committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-05-14 13:34:25 -0700 |
commit | bee160b31be9e09eeab83f62d26ac331f08955fa (patch) | |
tree | e0446c57d900f30d17419758c3ea3b37c24ded4a /src/mesa/drivers/dri/i965/brw_wm_state.c | |
parent | 7be100ac9af52b1ab5e2c34b45aba0d66304d55a (diff) | |
download | external_mesa3d-bee160b31be9e09eeab83f62d26ac331f08955fa.zip external_mesa3d-bee160b31be9e09eeab83f62d26ac331f08955fa.tar.gz external_mesa3d-bee160b31be9e09eeab83f62d26ac331f08955fa.tar.bz2 |
i965/fs: Organize prog_data by ksp number rather than SIMD width
The hardware packets organize kernel pointers and GRF start by slots that
don't map directly to dispatch width. This means that all of the state
setup code has to re-arrange the data from prog_data into these slots.
This logic has been duplicated 4 times in the GL driver and one more time
in the Vulkan driver. Let's just put it all in brw_fs.cpp.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_state.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_state.c | 31 |
1 files changed, 10 insertions, 21 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 91b35cd..bf1bdc9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -86,48 +86,37 @@ brw_upload_wm_unit(struct brw_context *brw) sizeof(*wm), 32, &brw->wm.base.state_offset); memset(wm, 0, sizeof(*wm)); - if (prog_data->prog_offset_16) { + if (prog_data->dispatch_8 && prog_data->dispatch_16) { /* These two fields should be the same pre-gen6, which is why we * only have one hardware field to program for both dispatch * widths. */ assert(prog_data->base.dispatch_grf_start_reg == - prog_data->dispatch_grf_start_reg_16); + prog_data->dispatch_grf_start_reg_2); } /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */ - if (prog_data->no_8) { - wm->wm5.enable_16_pix = 1; - wm->thread0.grf_reg_count = prog_data->reg_blocks_16; - wm->thread0.kernel_start_pointer = - brw_program_reloc(brw, - brw->wm.base.state_offset + - offsetof(struct brw_wm_unit_state, thread0), - brw->wm.base.prog_offset + - prog_data->prog_offset_16 + - (prog_data->reg_blocks_16 << 1)) >> 6; - - } else { - wm->thread0.grf_reg_count = prog_data->reg_blocks; - wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_16; - - wm->wm5.enable_8_pix = 1; - if (prog_data->prog_offset_16) - wm->wm5.enable_16_pix = 1; + wm->wm5.enable_8_pix = prog_data->dispatch_8; + wm->wm5.enable_16_pix = prog_data->dispatch_16; + if (prog_data->dispatch_8 || prog_data->dispatch_16) { + wm->thread0.grf_reg_count = prog_data->reg_blocks_0; wm->thread0.kernel_start_pointer = brw_program_reloc(brw, brw->wm.base.state_offset + offsetof(struct brw_wm_unit_state, thread0), brw->wm.base.prog_offset + (wm->thread0.grf_reg_count << 1)) >> 6; + } + if (prog_data->prog_offset_2) { + wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_2; wm->wm9.kernel_start_pointer_2 = brw_program_reloc(brw, brw->wm.base.state_offset + offsetof(struct brw_wm_unit_state, wm9), brw->wm.base.prog_offset + - prog_data->prog_offset_16 + + prog_data->prog_offset_2 + (wm->wm9.grf_reg_count_2 << 1)) >> 6; } |