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| author | Kenneth Graunke <kenneth@whitecape.org> | 2014-11-30 01:41:15 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2014-12-04 15:04:35 -0800 |
| commit | d300e58db0db8e44bd430bfc22d612355e4aab31 (patch) | |
| tree | 7031ea3d536a9b320b5c6f90b1cffba0ade6046e /src/mesa/drivers/dri/i965/brw_wm_state.c | |
| parent | 8daf3c53c7df806f7302446acb8a58d391f69779 (diff) | |
| download | external_mesa3d-d300e58db0db8e44bd430bfc22d612355e4aab31.zip external_mesa3d-d300e58db0db8e44bd430bfc22d612355e4aab31.tar.gz external_mesa3d-d300e58db0db8e44bd430bfc22d612355e4aab31.tar.bz2 | |
i965: Make Gen4-5 and Gen8+ ALT checks use ctx->_Shader too.
Commit c0347705 changed the Gen6-7 code to use ctx->_Shader rather than
ctx->Shader, but neglected to change the Gen4-5 or Gen8+ code.
This might fix SSO related bugs, but ALT mode is only used for ARB
programs, so if there's an actual problem, it's likely no one would
run into it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 12cbc72..d2903c7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -119,7 +119,7 @@ brw_upload_wm_unit(struct brw_context *brw) * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check * to differentiate between the GLSL and non-GLSL cases. */ - if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) + if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; else wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754; |