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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-01-13 09:50:37 -0800 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-01-22 10:21:07 -0800 |
| commit | 117a1d69de84c6cb7d895ce7e157f434facde7c9 (patch) | |
| tree | 25c0f383435cedb7e55356f59d4015119d336856 /src/mesa/drivers/dri/i965/brw_wm_surface_state.c | |
| parent | 404660e3c7bc6d13ae1d40185a02bfff6b956ac9 (diff) | |
| download | external_mesa3d-117a1d69de84c6cb7d895ce7e157f434facde7c9.zip external_mesa3d-117a1d69de84c6cb7d895ce7e157f434facde7c9.tar.gz external_mesa3d-117a1d69de84c6cb7d895ce7e157f434facde7c9.tar.bz2 | |
i965: Apply the miptree offset to surface state for renderbuffers
Previously, we were completely ignoring the mt->offset field for
renderbuffers. While it does have some alignment constraints, it is valid
to use it. This patch adds the code to each of the 4 surface state setup
functions to handle it.
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 85a08d5..bf7936c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -658,8 +658,9 @@ brw_update_renderbuffer_surface(struct brw_context *brw, format << BRW_SURFACE_FORMAT_SHIFT); /* reloc */ + assert(mt->offset % mt->cpp == 0); surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) + - mt->bo->offset64); + mt->bo->offset64 + mt->offset); surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); |