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author | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2014-05-07 10:49:50 +0300 |
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committer | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2014-05-15 21:39:32 +0300 |
commit | 6aefaa4eb23dec764a59f9e28bbe4a7d5036fdbf (patch) | |
tree | 86faef88354dfabfddb39220a9c23298cecf0de4 /src/mesa/drivers/dri/i965/brw_wm_surface_state.c | |
parent | 103057b2b7c0cf26c28b40fe5802acb8c6195c77 (diff) | |
download | external_mesa3d-6aefaa4eb23dec764a59f9e28bbe4a7d5036fdbf.zip external_mesa3d-6aefaa4eb23dec764a59f9e28bbe4a7d5036fdbf.tar.gz external_mesa3d-6aefaa4eb23dec764a59f9e28bbe4a7d5036fdbf.tar.bz2 |
i965/wm: Surface state overrides for configuring w-tiled as y-tiled
v2: Use intel_mipmap_tree::total_width in order to get correct alignment
automatically. Also use "mt->total_height / mt->physical_depth0" as
surface height allowing hardware to offset to correct slice.
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_surface_state.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 054467c..c9d9614 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -101,6 +101,30 @@ brw_get_surface_num_multisamples(unsigned num_samples) return BRW_SURFACE_MULTISAMPLECOUNT_1; } +void +brw_configure_w_tiled(const struct intel_mipmap_tree *mt, + bool is_render_target, + unsigned *width, unsigned *height, + unsigned *pitch, uint32_t *tiling, unsigned *format) +{ + static const unsigned halign_stencil = 8; + + /* In Y-tiling row is twice as wide as in W-tiling, and subsequently + * there are half as many rows. + * In addition, mip-levels are accessed manually by the program and + * therefore the surface is setup to cover all the mip-levels for one slice. + * (Hardware is still used to access individual slices). + */ + *tiling = I915_TILING_Y; + *pitch = mt->pitch * 2; + *width = ALIGN(mt->total_width, halign_stencil) * 2; + *height = (mt->total_height / mt->physical_depth0) / 2; + + if (is_render_target) { + *format = BRW_SURFACEFORMAT_R8_UINT; + } +} + /** * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle |