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| author | Jordan Justen <jordan.l.justen@intel.com> | 2014-09-03 14:28:59 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2014-09-04 23:06:27 -0700 |
| commit | 864c463485aafaa2802b18a7427f8b75dc96e3ef (patch) | |
| tree | a8b41434cd3b5b13fff67e85ae54c95fc5f7c62e /src/mesa/drivers/dri/i965/brw_wm_surface_state.c | |
| parent | 5d8f40a53a58c984906bc6509f01e31cc41ed1da (diff) | |
| download | external_mesa3d-864c463485aafaa2802b18a7427f8b75dc96e3ef.zip external_mesa3d-864c463485aafaa2802b18a7427f8b75dc96e3ef.tar.gz external_mesa3d-864c463485aafaa2802b18a7427f8b75dc96e3ef.tar.bz2 | |
Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404
Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
c5bdf9be1eca190417998d548fd140c1eca37a54
Conflicts:
src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
6f56e1424d923fd80c84090fbf4506c9eaaffea1
Conflicts:
src/mesa/drivers/dri/i965/brw_blorp.cpp
src/mesa/drivers/dri/i965/brw_state_cache.c
src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
88e3d404dad009d8cff5124cf8acee7daeaceb64
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index cf197c1..4a3111a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -729,7 +729,7 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw) } else { brw->vtbl.update_null_renderbuffer_surface(brw, 0); } - SET_DIRTY_BIT(brw, BRW_NEW_SURFACES); + brw->state.dirty.brw |= BRW_NEW_SURFACES; } const struct brw_tracked_state brw_renderbuffer_surfaces = { @@ -817,7 +817,7 @@ brw_update_texture_surfaces(struct brw_context *brw) update_stage_texture_surfaces(brw, fs, &brw->wm.base, true); } - SET_DIRTY_BIT(brw, BRW_NEW_SURFACES); + brw->state.dirty.brw |= BRW_NEW_SURFACES; } const struct brw_tracked_state brw_texture_surfaces = { @@ -869,7 +869,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, } if (shader->NumUniformBlocks) - SET_DIRTY_BIT(brw, BRW_NEW_SURFACES); + brw->state.dirty.brw |= BRW_NEW_SURFACES; } static void @@ -920,7 +920,7 @@ brw_upload_abo_surfaces(struct brw_context *brw, } if (prog->NumUniformBlocks) - SET_DIRTY_BIT(brw, BRW_NEW_SURFACES); + brw->state.dirty.brw |= BRW_NEW_SURFACES; } static void |