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authorJordan Justen <jordan.l.justen@intel.com>2013-07-09 15:24:56 -0700
committerJordan Justen <jordan.l.justen@intel.com>2014-08-15 20:11:41 -0700
commit039eb81abf4fab94e787ddd4d5ca4133f7af9c1c (patch)
tree5fac62501363ee6123b81467cdbb159e5b344436 /src/mesa/drivers/dri/i965/gen6_depth_state.c
parentcfa19af966f52a153502f8296493b7b08960f7f5 (diff)
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i965/gen6 depth surface: calculate minimum array element being rendered
(a23cfb8 for gen6) In layered rendering this will be 0. Otherwise it will be the selected slice. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_depth_state.c')
-rw-r--r--src/mesa/drivers/dri/i965/gen6_depth_state.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 9e03577..ec910f2 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -98,6 +98,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
break;
}
+ const unsigned min_array_element = irb ? irb->mt_layer : 0;
+
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
BEGIN_BATCH(7);