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author | Kenneth Graunke <kenneth@whitecape.org> | 2013-07-06 00:36:46 -0700 |
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committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-07-09 14:09:34 -0700 |
commit | 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d (patch) | |
tree | ddad922e67aee2521ea03acb27bcf38085d836c8 /src/mesa/drivers/dri/i965/gen6_queryobj.c | |
parent | 2e26afb37b83effe44b218d5b2a305020b8ad22f (diff) | |
download | external_mesa3d-53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d.zip external_mesa3d-53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d.tar.gz external_mesa3d-53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d.tar.bz2 |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_queryobj.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/gen6_queryobj.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index 8143630..6f4f6f5 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -45,9 +45,8 @@ static void write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx) { - struct intel_context *intel = &brw->intel; /* Emit workaround flushes: */ - if (intel->gen == 6) { + if (brw->gen == 6) { /* The timestamp write below is a non-zero post-sync op, which on * Gen6 necessitates a CS stall. CS stalls need stall at scoreboard * set. See the comments for intel_emit_post_sync_nonzero_flush(). @@ -78,9 +77,8 @@ write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx) static void write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx) { - struct intel_context *intel = &brw->intel; /* Emit Sandybridge workaround flush: */ - if (intel->gen == 6) + if (brw->gen == 6) intel_emit_post_sync_nonzero_flush(brw); BEGIN_BATCH(5); @@ -107,8 +105,7 @@ static void write_reg(struct brw_context *brw, drm_intel_bo *query_bo, uint32_t reg, int idx) { - struct intel_context *intel = &brw->intel; - assert(intel->gen >= 6); + assert(brw->gen >= 6); intel_batchbuffer_emit_mi_flush(brw); @@ -141,8 +138,7 @@ static void write_xfb_primitives_written(struct brw_context *brw, drm_intel_bo *query_bo, int idx) { - struct intel_context *intel = &brw->intel; - if (intel->gen >= 7) { + if (brw->gen >= 7) { write_reg(brw, query_bo, SO_NUM_PRIMS_WRITTEN0_IVB, idx); } else { write_reg(brw, query_bo, SO_NUM_PRIMS_WRITTEN, idx); |